1. Field of the Invention
The present invention relates to a technique for improving the degree of integration of a semiconductor integrated circuit device which is designed/fabricated by automatic arrangement/wiring or the like, and more particularly, it relates to a technique for improving the degree of integration of a semiconductor integrated circuit device which is provided with a driver circuit having high drivability.
2. Description of the Background Art
FIGS. 19(a) and 19(b) illustrate a structure of a macro cell which functions as a clock driver circuit. Referring to FIG. 19(a), numeral 1 denotes a driver circuit for driving a number of cells, symbol A denotes an input pin of the driver circuit 1, and symbols Y.sub.0 to Y.sub.n-1 denote N output pins of the driver circuit 1. The output pin number of this driver circuit 1 is N. When M flip-flops are connected to each of the output pins Y.sub.0 to Y.sub.n-1, for example, the fan-out is M by N.
FIG. 19(b) shows a macro cell which implements the driver circuit 1 shown in FIG. 19(a) and output signal lines thereof. Referring to FIG. 19(b), symbols Q1 to Q4 denote transistors for forming a macro cell implementing an example of the driver circuit 1 having N output pins shown in FIG. 19(a), symbol LA denotes a signal line serving as an input pin of the driver circuit, symbols LY.sub.0, LY.sub.1, . . . , LY.sub.n-2 and LY.sub.n-4 denote signal lines serving as output pins of the driver circuit, numeral 1 a denotes a part implementing the function of the driver circuit which is formed by the transistors etc., numeral 2 denotes the macro cell having the function of the driver circuit, numeral 3 denotes a signal line which is connected to drain electrodes of the transistors Q3 and Q4 provided in the part 1a implementing the function of the driver circuit, numeral 4a denotes a source line for supplying the macro cell 2 with a source potential VDD, and numeral 4b denotes a ground line for supplying the macro cell 2 with a ground potential GND. The macro cell 2 operates by potential difference between the source potential VDD and the ground potential GND.
As shown in FIG. 19(b), N output pins Y.sub.0, Y.sub.1, . . . , Y.sub.n-2 and Y.sub.n-1 are connected to the single output signal line 3, respectively, to extract an output of the driver circuit to the exterior of the macro cell 2. In the macro cell 2 for implementing a driver circuit having a large fan-out, the source line 4a and the ground line 4b which are formed by first layer aluminum wires are generally made larger in width than those in an ordinary macro cell.
A semiconductor integrated circuit device employing such a macro cell 2 is now described. FIG. 20(a) is a plan view showing a semiconductor chip for arranging the macro cell. Referring to FIG. 20(a), numeral 5 denotes a semiconductor chip which is provided with a semiconductor integrated circuit, numeral 6 denotes buffer areas which are provided in the peripheries of the semiconductor chip 5 for inputting or outputting power, signals etc. received from the exterior of the semiconductor chip 5, and numeral 7 denotes an internal region which is provided inside the buffer areas 6 of the semiconductor chip 5 for arranging and wiring various cells. In general, terminals for inputting/outputting signals etc. from/to the exterior are mounted on the semiconductor chip 5 by die bonding or the like, and this semiconductor chip 5 is sealed in a package to complete a semiconductor integrated circuit device.
FIG. 20(b) illustrates a part of the internal region 7 in an enlarged manner. An upper column 8a is a transistor column formed by a plurality of P-channel MOS transistors which are aligned with each other, and a lower column 8b is a transistor column formed by a plurality of N-channel MOS transistors which are aligned with each other. Numeral 8c denotes gate electrodes of P-channel MOS transistors, numeral 8d denotes diffusion areas serving as sources or drains of the P-channel MOS transistors, numeral 8e denotes gate electrodes of the N-channel MOS transistors, and numeral 8f denotes diffusion areas serving as sources or drains of the N-channel MOS transistors. It is possible to obtain a macro cell having various functions by connecting the gate electrodes 8c and 8e and the diffusion areas 8d and 8f using wiring layers provided on the semiconductor chip 5 and carrying out wiring within the cells.
FIG. 21(a) is a plan view showing the macro cell 2 in the semiconductor chip 5, appearing in FIG. 19(b), which is provided with a source line for feeding the macro cell 2, and a ground line. Referring to FIG. 21(a), numeral 9 denotes a macro cell column of the internal region 7 which is provided with the macro cell 2, numeral 10a denotes source lines which are formed by second layer aluminum wires, numeral 10b denotes feeding ground lines which are formed by second layer aluminum wires, numeral 11 denotes first layer aluminum wires for connecting the macro cell 2 with respective cells, and numeral 12 denotes the cells which are driven by the macro cell 2. FIG. 21(b) illustrates a part of the internal region 7 in an enlarged manner.
In general, the source line 4a and the ground line 4b provided in the macro cell 2 having the function of a large fan-out driver circuit or the like are arranged to be directly connected with the source and ground lines 10a and 10b, to cause no electromigration of the output signal lines. Further, the same numbers of cells 12 to be driven are generally connected to the N output pins of the macro cell 2 to reduce difference in load capacitance and resistance between the N output pins, thereby facilitating a layout for reducing skews between the output pins.
In the conventional semiconductor integrated circuit device having the aforementioned structure, however, the source line 4a and the ground line 4b of the large fan-out macro cell 2 provided along the macro cell column which is formed by the first layer aluminum wires must be made larger in width than those in other macro cells. Therefore, the area of the semiconductor chip 5 is increased, for example, such that all macro cell columns between a plurality of feeder lines which are formed by source lines 10a and ground lines 10b are employed.